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41 db range, 1 db step size, programmable dual vga data sheet ad8372 rev. c document feedback information furnished by analog devices is believed to be accurate an d reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of pat ents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or pa tent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2007C2017 analog devices, inc. all rights reserved. technical support www.analog.com features dual independent digitally controlled vga differential input and output 150 differential input open-collector differential output 7.8 db noise figure to 100 mhz @ maximum gain hd2/hd3 better than 77 dbc for 1 v p-p differential output ?3 db bandwidth of 130 mhz 41 db gain range 1 db step size 0.2 db serial 8-bit bidirectional spi control interface wide input dynamic range pin-programmable output stage power-down feature single 5 v supply: 106 ma per channel 32-lead lfcsp, 5 mm 5 mm package applications differential adc drivers cmts upstream direct sampling receivers catv modem signal scaling generic rf/if gain stages single-ended-to-differential conversion functional block diagram enb1 ipc1 inc1 clk1 rxt1 lch1 ipc2 inc2 enb2 sdi1 sdo1 ref1 opc1 onc1 rxt2 sdi2 lch2 opc2 ref2 onc2 sdo2 clk2 postamp channel 1 postamp channel 2 registers and gain decoder ad8372 07051-001 figure 1. general description the ad8372 is a dual, digitally controlled, variable gain amplifier (vga) that provides precise gain control, high ip3, and low noise figure. the excellent distortion performance and moderate signal bandwidth make the ad8372 a suitable gain control device for a variety of multichannel receiver applications. for wide input dynamic range applications, the ad8372 provides a broad 41 db gain range. the gain is programmed through a bidirectional 4-pin serial interface. the serial inter- face consists of a clock, latch, data input, and data output lines for each channel. the ad8372 provides the ability to set the transconductance of the output stage using a single external resistor. the rxt1 and rxt2 pins provide a band gap derived stable reference voltage of 1.56 v. typically 2.0 k shunt resistors to ground are used to set the maximum gain to a nominal value of 31 db. the current setting resistors can be adjusted to manipulate the gain and distortion performance of each channel. this is a flexible feature in applications where it is desirable to trade off distortion performance for lower power consumption. the ad8372 is powered on by applying the appropriate logic level to the enb1, enb2 pins. when powered down, the ad8372 consumes less than 2.6 ma and offers excellent input-to-output isolation. the gain setting is preserved when powered down. fabricated on an analog devices, inc., high frequency bicmos process, the ad8372 provides precise gain adjustment capabilities with good distortion performance. the quiescent current of the ad8372 is typically 106 ma per channel. the ad8372 amplifier comes in a compact, thermally enhanced 5 mm 5 mm 32-lead lfcsp package and operates over the temperature range of ?40c to +85c.
ad8372 data sheet rev. c | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 s erial control interface timing ................................................. 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ..............................................8 theory of operation ...................................................................... 10 single - ended and differential signals ..................................... 10 passive filter techniques ........................................................... 10 digit al gain control .................................................................. 10 driving analog - to - digital converters .................................... 10 evaluation board schematic ......................................................... 12 outline dimensions ....................................................................... 13 ordering guide .......................................................................... 13 revision history 9 /2017 ? rev. b to rev. c changed cp - 32 - 2 to cp - 32 -7 ...................................... throughout updated outli ne dimensions ....................................................... 13 changes to ordering guide .......................................................... 13 6/ 2011 ? rev. a to rev. b changes to table 4 ............................................................................ 6 changes to figure 4 and table 5 ..................................................... 7 added exposed pad notation to outline dimensions ............. 13 changes to ordering guide .......................................................... 13 5/ 2008 ? rev. 0 to rev. a changes to features and figure 1 ................................................... 1 changes to figure 2 and figure 3 ................................................... 5 changes to figure 9 .......................................................................... 8 changes to figure 16 ...................................................................... 12 11/2007 ? revision 0: initial version
data sheet ad8372 rev. c | pa ge 3 of 16 specifications v s = 5 v, t = 25c, z s = 150 ?, z l = 250 ? at 35 mhz, 1 v p - p differential output, rxt1 = r xt2 = 2.0 k , unless otherwise noted. table 1 . parameter conditions min typ max unit dynamic performance ? 3 db bandwidth v out < 1 v p - p, c load < 3pf 130 mhz input stage pin ipc1 , pin inc1, pin ipc2 , and pin inc2 maximum i nput s wing at e ach input p in 5 v p -p input resistance differential 150 common - mode input voltage 2.4 v cmrr gain code = 1x101010 (max gain) 55 db gain maximum voltage gain gain code = 1x101010 32 db minimum voltage gai n gain code = 1x000001 ?9 db gain step size from gain code 1x000001 to 1x101010 1.0 db gain step accuracy from gain code 1x000001 to 1x101010 0.3 db gain flatness gain code = 1x101010, from 5 mhz to 65mhz 0.7 db gain temperature sensitivity ga in code = 1x101010 7.5 mdb/ c step response for 6 db gain step, 10% settling 20 ns output stage pin opc 1, pin onc1, pin opc2, and pin onc2 output voltage swing at p1db, gain code = 1x101010 9 v p - p output resistance differential 3.5 k channel isolation measured at differential output for differential input applied to alternate channel 55 db noise/harmonic performance 5 mhz gain code = 1x101010 (max gain) noise figure 7.8 db second harmonic 79 dbc third harmoni c 91 dbc output ip3 32 dbm output 1 db compression point 18.2 dbm 35 mhz gain code = 1x101010 (max gain) noise figure 7.8 db second harmonic 79 dbc third harmonic 87 dbc output ip3 35 dbm output 1 db compression p oint 18.1 dbm 65 mhz gain code = 1x101010 (max gain) noise figure 7.9 db second harmonic 78 dbc third harmonic 85 dbc output ip3 35 dbm output 1 db compression point 17.9 dbm 85 mhz gain code = 1x101010 noise figur e 8.1 db second harmonic 77 dbc third harmonic 85 dbc output ip3 35 dbm output 1 db compression point 17. 7 dbm
ad8372 data sheet rev. c | page 4 of 16 parameter conditions min typ max unit power i nterface supply voltage 4.5 5.5 v quiescent current per channel thermal connection made to exposed paddl e under device 106 ma vs. temperature ? 40c t a + 85c 135 ma power - down current, b oth c hannels enb1 and enb2 low 1.2 ma vs. temperature ? 40c t a + 85c 1.3 ma enable interface pin enb1 and pin enb2 enable threshold minimum voltage to enable the device 0.8 v enb1, enb2 input bias current enb1, enb2 = 0 v 400 na gain control interface pin clk1, pin clk2, pin sdi1, pin sdi2, pin sdo1, pin sdo2, pin lch1, and pin lch2 v ih minimum voltage for a logic high 2.4 v input bias current 400 na serial port output f eedthrough worse - case feedthrough from clk1, clk2, sdi1, sdi2, sdo1, sdo2, lch1, lch2 to opc1 and onc2, or opc2 and onc2 ?60 db table 2 . gain code vs. voltage gain look - up table 8- bit binary gain code 1 voltage gain (db) rw dc 000000 < ?60 rw dc 000001 ?9 rw dc 000010 ?8 rw dc 000011 ?7 rw dc 000100 ?6 rw dc 000101 ?5 rw dc 000110 ?4 rw dc 000111 ?3 rw dc 001000 ?2 rw dc 001001 ?1 rw dc 001010 0 rw dc 001011 +1 rw dc 001100 +2 rw dc 001101 +3 rw dc 001110 +4 rw dc 001111 +5 rw dc 010000 +6 rw dc 010001 +7 rw dc 010010 +8 rw dc 010011 +9 rw dc 010100 +10 rw dc 010101 +11 1 rw is the read/write bit. rw = 0 for read mode; rw = 1 for write mode. dc is the don?t care bit. 8- bit binary gain code 1 voltage gain (db) rw dc 010110 +12 rw dc 010111 +13 rw dc 011000 +14 rw dc 011001 +15 rw dc 011010 +16 rw dc 011011 +17 rw dc 011100 +18 rw dc 011101 +19 rw dc 011110 +20 rw dc 011111 +21 rw dc 100000 +22 rw dc 100001 +23 rw dc 100010 +24 rw dc 100011 +25 rw dc 1001 00 +26 rw dc 100101 +27 rw dc 100110 +28 rw dc 100111 +29 rw dc 101000 +30 rw dc 101001 +31 rw dc 101010 +32 rw dc 101011 < ?60
data sheet ad8372 rev. c | pa ge 5 of 16 serial control interface timing 07051-003 don't care write bit lsb lsb + 1 lsb + 2 msb C 2 msb C 1 msb t dh t ds t lh t ls t pw t clk notes 1. the first sdi bit determines whether the part is writing to or reading from the internal gain word regis ter. for a write operation, the first bit should be a logic 1. the gain word bit is then registered into the sdi pin on conse cutive rising edges of the clock. clk1 or clk2 lch1 or lch2 sdi1 or sdi2 figure 2 . write mode timing diagram 07051-004 t lh t dh t ds t ls t pw t clk dc dc read bit dc dc dc dc dc lsb lsb + 1 lsb + 2 msb C 2 msb C 1 msb clk1 or clk2 lch1 or lch2 sdi1 or sdi2 sdo1 or sdo2 t d notes 1. the first sdi bit determines whether the part is writing to or reading from the internal gain word regis ter. for a read operation, the first bit should be a logic 0. the gain word bit is then updated at the sdo pin on conse cutive falling edges of the clock. figure 3 . read mode timing dia gram table 3 . serial programming timing parameters parameter min u nit clock pulse width (t pw ) 10 ns clock period (t ck ) 20 ns write mode setup time data vs. clock (t ds ) 0.0 ns hold time data vs. clock (t dh ) 1.6 ns setup time latch vs. clock (t ls ) ?1.8 ns hold time latch vs. clock (t lh ) 2.0 ns read mode clock to data out (t d ) 4.5 ns
ad8372 data sheet rev. c | page 6 of 16 absolute maximum rat ings table 4 . parameter rating supply voltage, v s 5.5 v enb1, enb2, sdi1, sdi2, sdo1, sdo2, clk1, clk2, lch1, lch2 dgdx ? 0.5 v to v s + 500 mv input voltage, v ipc1 , v inc1 , v ipc2 , v inc2 agd x ? 0.5 v to v s + 500 mv internal power dissipation 1.4 w ja (exposed p addle s oldered d own) 34.6 c/w 1, 2 jc (at e xposed p addle) 3.6 c/w 2 maximum junction temperature 150 c operating temperature range ? 40 c to +85 c storage temperature range ? 65 c to +150 c 1 still air. 2 all values are modeled using a standard 4 - layer jedec test board with the pad soldered to the board and thermal vias in the board. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other condi tions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. esd caution
data sheet ad8372 rev. c | page 7 of 16 pin configuration and fu nction descriptions pin 1 indicator dvs1 lch1 sdi1 clk1 clk2 sdi2 lch2 dvs2 notes 1. the exposed pad should be connected to agd1 and agd2. opc1 onc1 agd1 sdo1 sdo2 agd2 onc2 opc2 dgd2 inc2 ipc2 ref2 rxt2 agd2 enb2 av s2 dgd1 inc1 ipc1 ref1 rxt1 agd1 enb1 avs1 07051-002 2423 22 21 20 19 18 17 12 3 4 5 6 7 8 9 10 11 1213 14 15 16 3231 30 29 28 27 26 25 ad8372 top view (not to scale) figure 4. pin configuration table 5. pin function descriptions pin no. mnemonic description 1 dvs1 digital supply pin for channel 1 2 lch1 latch input for channel 1 3 sdi1 serial data input for channel 1 4 clk1 clock input for channel 1 5 clk2 clock input for channel 2 6 sdi2 serial data input for channel 2 7 lch2 serial data input for channel 2 latch input for channel 2 8 dvs2 digital supply pin for channel 2 9 dgd2 digital ground for channel 2 10 inc2 negative input for channel 2 11 ipc2 positive input for channel 2 12 ref2 reference voltage for channel 2 13 rxt2 external bias setting resistor connection for channel 2 14 agd2 analog ground for channel 2 15 enb2 chip enable pin for channel 2 16 avs2 analog supply pin for channel 2 17 opc2 positive output for channel 2 18 onc2 negative output for channel 2 19 agd2 analog ground for channel 2 20 sdo2 serial data output for channel 2 21 sdo1 serial data output for channel 1 22 agd1 analog ground for channel 1 23 onc1 negative output for channel 1 24 opc1 positive output for channel 1 25 avs1 analog supply pin for channel 1 26 enb1 chip enable pin for channel 1 27 agd1 analog ground for channel 1 28 rxt1 external bias setting resistor connection for channel 1 29 ref1 reference voltage for channel 1 30 ipc1 positive input for channel 1 31 inc1 negative input for channel 1 32 dgd1 digital ground for channel 1 epad exposed pad. the exposed pad should be connected to agd1 and agd2.
ad8372 data sheet rev. c | page 8 of 16 typical performance characteristics v s = 5 v, t a = 25c, z s = 150 , z l = 250 , 1 v p-p differential output, both channels enabled, unless otherwise noted. 07051-005 frequency (hz) voltage gain (db) C30 C20 C10 0 10 20 30 40 1m 10m 100m 1g figure 5. gain vs. frequency by gain code (all codes), differential in, differential out C100 C95 C90 C85 C80 C75 C70 C65 C 60 0 102030405060708090 hd3 07051-006 frequency (mhz) harmonic distortion (dbc) hd2 figure 6. 2 nd and 3 rd harmonic distortion 07051-007 0 10 20 30 40 50 60 70 80 90 100 0 102030405060708090 frequency (mhz) oip2/oip3 (dbm) oip3 C a v = 32 oip2 C a v = 32 oip3 C a v = 10 oip3 C a v = C9 oip2 C a v = 10 oip2 C a v = C9 figure 7. oip2 and oip3 15 16 17 18 19 20 +25c +85c C40c 07051-008 0 102030405060708090 frequency (mhz) output referred p1db (dbm) figure 8. p1db, maximum gain 0 7051-009 0 frequency (mhz) resistance ( ? ) 0 20 40 60 80 100 120 140 160 180 50 100 150 200 250 300 0 1 2 3 4 5 6 7 8 9 capacitance (pf) figure 9. input equivale nt parallel impedance 07051-010 frequency (mhz) cmrr (db) 0 10 20 30 40 50 60 70 0 102030405060708090100 figure 10. cmrr vs. frequency
data sheet ad8372 rev. c | page 9 of 16 0 5 10 15 20 25 30 35 40 45 50 20 40 60 80 100 120 140 160 180 200 a v = 10db a v = 20db a v = 32db 07051-012 0 frequency (mhz) noise figure (db) a v = 0db figure 11. noise fi gure vs. frequency C90 C80 C70 C60 C50 C40 C30 C20 C10 0 07051-013 frequency (hz) (db) 1m 10m 100m 1g figure 12. isolation, input to opposite output at maximum gain (to calculate output to output gain, subtract 29 db from this plot) 07051-011 20ns/div figure 13. ad8372 response to 6 db step change in gain (gain register setting 36 to setting 42); falling edge shown is serial clock input edge
ad8372 data sheet rev. c | page 10 of 16 theory of operation the ad8372 is a dual differential variable gain amplifier. each amplif ier consists of a 15 0 digitally controlled 6 db attenuator followed by a 1 db vernier and a fixed gain transconductance amplifier. the differential output on each amplifier consists of a pair of open - collector transistors. it is recommended that each open - collector output b e biased to +5 v with a high value inductor. a 33 h inductor, such as the coilcraft ? 1812ls - 333xjl, is an excellent choice for this component. a 250 resistor should be placed across the differential outputs to provide a current - to - voltage conversion an d as a source impedance for passive filtering, post ad8372. the gain for each side is based on a 250 differential load and varies as the r load changes per the following equations: gain = 20log( r load /250), for voltage gain gain = 10log( r load /250), for power gain the dependency of the gain on the load is due to the open - collector output stage that is biased using external chokes. the inductance of the chokes and the resistance of the load deter - mine the low frequency pole of the amplifier. the high frequ ency pole is set by the parasitic capacitance of the chokes and outputs in parallel with the output resistance. the total supply current of 106 ma per side consists of 70 ma for the combined outputs and about 36 ma through the power supply pins. each side has an external resistor ( r ext ) to ground to set the trans conductance of the output stage . for optimum distortion, 106 ma total current per side is recommended, making the r ext value about 2.0 k. each side has a 2.4 v reference pin and that same common -m ode voltage appears on the inputs. this reference should be decoupled using a 0.1 f capacitor. the part can be powered down to less than 2.6 ma by setting the enb pin low for the appropriate side. the noise figure of the ad8372 is 7.8 db at maximum gain and increases as the gain is reduced. the increase in noise figure is equal to the reduction in gain. the linearity of the part measured at the output is first - order independent of the gain setting. layout considerations should include minimizing capacita nce on the outputs by avoiding ground planes under the chokes, and equalizing the output line lengths for phase balance. single - ended and differenti al signals the ad8372 is designed to be used by applying differential signals to the inputs and using the di fferential output drive of the device to drive the next device in the signal chain. the excellent distortion performance of the ad8372 is due primarily to the use of differential signaling techniques to cancel various distortion components in the device. i n addi tion, all ac characterization i s done using differential signal paths. using this device with either the input or the output in a single - ended circuit significantly degrades the overall performance of the ad8372. passive filter techn iques the ad8372 has a 100 differential input impedance. for optimal performance, the differential output load should be 250 . when designing passive filters around the ad8372, these impedances must be taken into account. digital gain control the digital gain control i nterface consists of the following pins: sdi, sdo, clk, and latch. the interface is active when the latch pin is shifted low. gain words are written into the ad8372 via the sdi pin, and read back from the sdo pin. the first bit clocke d into the data input pin deter mines whether the interface is in write or read mode. the second bit is a dont care bit, while the remaining six bits program the gai n. in read mode, the sdo pin clocks out the 6 - bit gain word, lsb to msb. the gain can be programmed between ?9 db and 32 db in 1 db steps. timing details are given in figure 2 a nd figure 3 . the gain code is given in table 2. driving analog - to - digital converters the ad8372 i s designed with t he intention of driving high speed, high dynamic range adcs. the circuit in figure 14 represents a simplified front end of one - half of the ad8372 dual vga driving an ad9445 14 - bit, 125 mhz analog - to - digital converter (adc) . the input of the ad8372 is driven differentially using a 1:3 impedance ratio transformer, which also matches the 150 input resistance to a 50 source. the open - collector outputs are biased through the 33 h induct ors and are ac - coupled from the 142 load resistors that, in parallel with the 2 k input resistance of the adc, provide a 250 load for gain accuracy. the adc is ac - coupled from the 142 resistors to negate a dc effect on the input common - mode voltage of the ad9445. including the series 33 resistors improves the isolation of the ad8372 from the switching currents caused by the adc input sample and hold. the ad9445 represents a 2 k differential load and requires a 2 v p - p signal when vref = 1 v for a full - scale output. this circuit provides variable gain, isolation, and source matching for the ad9445. using this circuit with the ad8372 in a gain of 32 db (maximum gain), an sfdr performance of 7 4.5 dbc is achieved at 85 mhz (s ee figure 15 ).
data sheet ad8372 rev. c | page 11 of 16 07051-018 0.1f 0.1f 33h 142 ? 33 ? 33 ? 142 ? 5v 5 v 50 ? ac 1:3 ckl1 sd01 ena1 ? ad8372 vga 0.1f 0.1f 0.1f 0.1f 33h 5v vin+ vinC ad9445 14-bit adc 14 figure 14. ad8372 driving an ad9445 adc C150 C140 C130 C120 C110 C100 C80 C70C90 C60 C40 C30C50 C20 C10 0 07051-019 frequency (mhz) (dbc) 5.25 10.50 15.75 21.00 26.25 31.50 36.75 42.00 47.25 52.50 0 5 6 4 1 2 3 encode: 105mhz samples: 32768 analog: 19.8766mhz fund: C1.053dbfs 2nd: C74.55dbc 3rd: C86.45dbc 4th: C91.35dbc 5th: C89.57dbc 6th: C91.15dbc snr: 58.12dbc snrfs: 59.18dbc thd: C73.99dbc sinad: 58.01dbc sfdr: 74.73dbc wo spur: C85.5dbc noise floor: C101.3db fund leak: 100 harm leak: 3 dc leak: 6 figure 15. 74.5 dbc sfdr performance of the ad8372 driving the ad9445 adc
ad8372 data sheet rev. c | page 12 of 16 evaluation board sch ematic 07051-014 ad8372 char bd r0603 a gnd a gnd a gnd a gnd a gnd a gnd 0 r0603 a gnd a gnd a gnd a gnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd 0 r0603 a gnd a gnd a gnd a gnd a gnd r0603 c0603 0.1uf a gnd c0603 0.1uf tbd c0603 tbd c0603 tbd c0603 tbd c0603 tbd c0603 tbd c0603 c0603 0.1uf c0603 0.1uf c0603 0.1uf a gnd a gnd a gnd a gnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd r0603 a gnd dgnd dgnd a gnd a gnd te s tloop orange te s tloop red dgnd sec pri sec pri sec pri a gnd 0 r0603 a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd dvs1 dvs2 ocp2 onc2 agd2 sdo2 sdo1 agd1 onc1 opc1 avs1 enb1 agd1 rxt1 ref1 ipc1 inc1 dgd1 avs2 enb2 adg2 rxt2 ref2 ipc2 inc2 dgd2 lch2 clk2 clk1 sdi1 lch1 sdi2 c0603 0.1uf c0603 0.1uf c0603 0.1uf c0603 0.1uf 0 r0603 r0603 r0603 0 r0603 0 r0603 a gnd c0603 c0603 r0603 sec pri r0603 r0603 r0603 r0603 0 r0603 tbd r0603 0 r0603 tbd r0603 0 r0603 0 r0603 r0603 r0603 tbd c0603 tbd c0603 r0603 r0603 r0603 r0603 r0603 r0603 r0603 r0603 r0603 r0603 r0603 r0603 r0603 r0603 1:3 100 ohms 75 ohms 75 ohms 75 ohms 75 ohms 75 ohms 100 ohms 100 ohms 100 ohms 100 ohms 100 ohms 50 ohms 50 ohms 50 ohms 50 ohms 50 ohms 50 ohms 50 ohms 75 ohms 75 ohms 75 ohms 100 ohms 100 ohms 100 ohms 100 ohms 50 ohms 1:3 c12 1nf c0603 r46 24.9_1% r45 24.9_1% r43 24.9_1% r44 24.9_1% r38 113 r37 113 r36 113 r35 113 1812 l2 33uh r21 tbd r30 0 r29 0 r27 0 r28 0 r26 tbd 33uh l4 1812 1812 l3 33uh c10 c9 r48 tbd r1 2k r19 r20 r33 r42 r34 r41 2k r2 r39 0 r12 tbd r31 tbd 3 2 1 46 t2 r15 0 c1 1nf c8 1nf h1-7 0 r0603 r13 h1-15 agnd w3 w2 h1-15 r23 33uh l1 1812 r22 r40 tbd r32 tbd h1-12 h1-6 h1-1 agnd ipc2 inc2 inc1 h1-15 r24 h1-15 c22 c24 c26 c25 1 10 11 12 13 14 15 16 17 18 19 2 20 21 22 23 24 25 26 272829 3 3031 32 45 6 78 9 z1 ad8372 opc2 c29 0.1uf c0603 c0603 0.1uf c28 c18 0.1uf c0603 c0603 0.1uf c11 c32 0.1uf c0603 h1-15 ipc1 r3 10 p1 b20 p2 b19 p2 b18 p2 b17 p2 b16 p2 b15 p2 b14 p2 h1-4 32 1 4 6 t1 32 1 46 t3 6 4 1 2 3 t4 c1206 l6 tbd tbd l5 c1206 14 p1 15 p1 16 p1 17 p1 18 p1 19 p1 20 p1 21 p1 22 p1 23 p1 24 p1 25 p1 13 p1 12 p1 11 p1 9 p1 8p1 7 p1 6 p1 5p1 4 p1 3p1 2p1 1 p1 h1-1 h1-15 vdd vss c33 10uf 3528 dgnd agnd c0603 0.1uf c14 c15 0.1uf c0603 c13 0.1uf c0603 10k r18 onc1 opc1 onc2 sdo2 h1-12 sdo1 r14 r0603 0 c0603 0.1uf c17 h1-5 h1-4 h1-3 h1-1 h1-11 h1-10 h1-9 h1-1 agnd agnd agnd 0 r0603 r7 r8 r0603 0 c19 c23 0 r0603 r4 c20 r5 r0603 0 c2 c3 0 r0603 r6 c5 c4 r10 r0603 0 c7 c6 0 r0603 r9 c21 r11 r0603 0 c27 r17 10k w1 sdo1 sdo2 c0603 1nf c16 r16 h1-3 h1-5 h1-6 h1-6 3528 10uf c34 a1 p2 a2 p2 a3 p2 a4 p2 a5 p2 a6 p2 a7 p2 a8 p2 a9 p2 a10 p2 a11 p2 a12 p2 a13 p2 a14 p2 a15 p2 a16 p2 a17 p2 a18 p2 a19 p2 a20 p2 b1 p2 b2 p2 b3 p2 b4 p2 b5 p2 b6 p2 b7 p2 b8 p2 b9 p2 b10 p2 b11 p2 b12 p2 b13 p2 h1-8 h1-12 h1-10 h1-11 h1-7 h1-9 h1-14 h1-4 h1-16 h1-15 h1-3 h1-5 h1-6 h1-13 h1-8 h1-12 h1-10 h1-11 h1-7 h1-9 h1-14 h1-4 h1-16 h1-15 h1-3 h1-5 h1-6 h1-13 h1-11 h1-12 h1-9 h1-10 r25 h1-1 h1-12 h1-6 h1-15 w4 w5 w6 w7 w8 agnd tbd r47 h1-7 h1-13 h1-13 r49 r0603 0 figure 16 . ad8372 evaluation board schematic
data sheet ad8372 rev. c | pa ge 13 of 16 outline dimensions 3.25 3.10 sq 2.95 0.80 0.75 0.70 1 0.50 bsc bottom view top view pin 1 indic at or 32 9 16 17 24 25 8 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.50 0.40 0.30 0.25 min 02-22-2017-a compliant to jedec standards mo-220- whhd pkg-003898 sea ting plane exposed pad side view pin 1 indic at or area options (see detail a) detail a (jedec 95) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 17 . 32 - lead lead frame chip scale package [lfcsp] 5 mm 5 mm body and 0.75 mm package height (cp - 32 -7) dimensions shown in millimeters ordering guide model 1 temperature r ange package description package option ordering quantity ad8372acpz - wp ?40c to +85c 32 - lead lead frame chip scale package [lfcsp], waffle pack cp - 32 -7 36 ad8372acpz - r7 ?40c to +85c 32 - lead lead frame chip scale package [lfcsp], 7? tape and reel cp- 32 -7 1,500 ad8372 - evalz evaluation board 1 z = rohs compliant part.
ad8372 data sheet rev. c | page 14 of 16 notes
data sheet ad8372 rev. c | pa ge 15 of 16 notes
ad8372 data sheet rev. c | page 16 of 16 notes ? 2007 ? 2017 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d07051 -0- 9/17(c)

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